Many SOCs today contain both digital and analog embedded cores. Even thoughthe test cost for such mixed-signal SOCs is significantly higher than that fordigital SOCs, most prior research in this area has focused exclusively ondigital cores. We propose a low-cost test development methodology formixed-signal SOCs that allows the analog and digital cores to be tested in aunified manner, thereby minimizing the overall test cost. The analog cores inthe SOC are wrapped such that they can be accessed using a digital test accessmechanism (TAM). We evaluate the impact of the use of analog test wrappers onarea overhead and test time. To reduce area overhead, we present an analog testwrapper optimization technique, which is then combined with TAM optimization ina cost-oriented heuristic approach for test scheduling. We also demonstrate thefeasibility of using analog wrappers by presenting transistor-level simulationsfor an analog wrapper and a representative core. We present experimentalresults on test scheduling for an ITC'02 benchmark SOC that has been augmentedwith five analog cores.
展开▼
